Executive Appointment Mandate
ID: EX-1008588017355
Design Verification Engineer
Compensation Bracket
Salary Disclosed on Application
Tenure & Discipline
Executive Full-Time
Jurisdiction
United States
Statutory Visa Pathway
US Immigrant / H-1B
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Executive Mandate Specification
Summary
Posted: Aug 9, 2022
Weekly Hours: 35
Role Number:200224171
Do your life’s best work here - with the whole world watching. Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The Design Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a strong foundation in verification methodology will be used to close testing coverage with high confidence.
Key Qualifications
- Expertise with verification languages such as SystemVerilog, Specman or Vera and verification methodologies such as UVM/OVM is a plus.
- Experience of working in complex ASIC or SoC designs
- Expertise with HDL simulators & waveform viewers
- Experience defining coverage space, writing coverage model, analyzing results
- Experience working under strict schedule deadlines with the ability to handle multiple priorities
- Graphics architecture and programming (OpenGL/OpenCL) highly desired. Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.
- Experience with scripting languages like Python, Go, Perl or Ruby is a plus
- Excellent communication skills and ability to collaborate
Description
Use SystemVerilog, UVM and C++ with industry-leading simulation tools and methodologies to verify complex GPU designs . Develop verification plans in coordination with design leads and architects Create and maintain verification test bench components and environments Generate directed and directed random tests Run simulations and debug design and environment issues Build functional coverage points, analyze coverage, and improve test environment to target coverage holes Build automated verification flows for block verification Work with other block and core level engineers to ensure seamless verification flow
Education & Experience
BS/MS CE or EE or related field,
Additional Requirements
- Successful candidates based in Cambridge will be working as part of a wider Cambridge / St Albans team. Travel to St Albans will be required from time to time .
Statutory Executive Benefits & Governance
- Executive Health, Vision & Dental Coverage with Global Provider Options
- Corporate Pension Auto-Enrolment / 401(k) Retirement Plan with Fiduciary Matching
- Annual Discretionary Performance Incentive & Long-Term Equity Participation
- Executive Leave Allotment, Statutory Holidays & Dedicated Health Care Reserves
- US Department of Labor & E-Verify Work Authorization Sponsorship
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